Looking at the Gotek read, it does not have a pause after the Ready is asserted. Are there too many read "bits/bumps"?
Do you transmit data once the Ready signal is asserted?
Attachments
Gotek - Read Cycle - Ready and Read Data .jpg (188.09 KiB) Viewed 19268 times
AMSynths wrote: Thu Aug 29, 2019 5:15 pm
Downloaded the correct files...but I/O Error 3 on both
On 001 and 002 ? ok, very strange... Unless the Error 3 mean that there is a too long blank time on the serial link, which may be fine regarding the service manual notes.
AMSynths wrote: Thu Aug 29, 2019 5:27 pm
Looking at the Gotek read, it does not have a pause after the Ready is asserted. Are there too many read "bits/bumps"?
Do you transmit data once the Ready signal is asserted?
On the last images i post it should have a blank. Maybe it is wrongly placed ? Can you dezoom ? was 20ms/per division, now it's 200us/div
The Real QD is not sending a constant stream of data with the same number of bumps...and does not look like the "predictable" Gotek read pattern
See trace...
Attachments
RealQD - Read Cycle Detail - Ready and Read Data .jpg (84.9 KiB) Viewed 19261 times
Last edited by AMSynths on Thu Aug 29, 2019 5:42 pm, edited 2 times in total.
AMSynths wrote: Thu Aug 29, 2019 5:38 pm
The Real QD is not sending a constant stream of data with the same number of bumps...and does not like like the Gotek read
See trace...
Sure , this region is unformatted so the data are "random". I can add this in the image since the firmware support weak bits emulation but i am not sure if this the right way to fix the issue.
Do you see the blank part with the gotek with the 20ms per div ?
Shouldn't the Gotek data start after the Ready is asserted with a pause?
Its this early set of data which the sampler reads to check its a real QD, its failing as soon as it reads some data.
Take a look...there is no pause after Ready assert and the data looks very different.
Looks like the quick disk chip cannot sync to the data stream as its immediately throwing an error
Attachments
Gotek - Read Cycle Detail - Ready and Read Data .jpg (96.69 KiB) Viewed 19254 times
AMSynths wrote: Thu Aug 29, 2019 5:52 pm
Take a look...there is no pause after Ready assert and the data looks very different.
Looks like the quick disk chip cannot sync to the data stream as its immediately throwing an error
You use 50us/div. Your screen with the blank was 20ms/div.