WD1770/1772 5 1/4 " Floppy Disk Controller/Formatter
DESCRIPTION
The WD1770 is a MOS LSI device which performs the functions of a 5 1/4 "
Floppy Disk Controller/Formatter. It is similar to its predecessor, the
WD179x but also contains a digital data separator and write precompensation
circuitry. The drive side of the interface needs no additional logic except
for buffers/receivers. Designed for 5 1/4 " single or double density
operation. The device contains a programmable Motor On signal.
The WD1770 is a low cost version of the FD179x Floppy Disk
Controller/Formatter. It is compatible with the 179x, but has a built-in
digital data separator and write precompensation circuits. A single read line
(notRD, pin 19) is the only input required to recover serial FM or MFM data
from the disk drive. The device has been specifically designed for control of
5 1/4 " floppy disk drives with data rates of 125 Kbits/sec (single density)
and 250 Kbits/sec (double density). In addition write precompensation of 125
Nsec from nominal can be enabled at any point through simple software
commands. Another programmable feature, Motor On, has been incorporated to
enable the spindle motor prior to operating a selected drive.
Two versions of the WD1770 are available. The standard version is compatible
with the 179x stepping rates, while the WD1772 offers stepping rates of 2, 3,
5 and 6 msec.
The processor interface consists of an 8-bit bidirectional bus for transfer
of status, data and commands. All host communication with the drive occurs
through these data lines. They are capable of driving one standard TTL load
or three "LS" loads.
+------+
notCS 1 28 INTRQ
R/notW 2 27 DRQ
A0 3 26 notDDEN
A1 4 25 notWPRT
DAL0 5 24 notIP
DAL1 6 1772 23 notTR00
DAL2 7 FDC 22 WD
DAL3 8 21 WG
DAL4 9 20 MO
DAL5 10 19 notRD
DAL6 11 18 CLK
DAL7 12 17 DIREC
notMR 13 16 STEP
GND 14 15 Vcc
+------+
ARCHITECTURE
The Floppy Disk Formatter block diagram is illustrated on page 4. The primary
sections include the parallel processor interface the the Floppy Disk
Interface.
Data Shift Register - This 8-bit register assembles serial data from the Read
Data input (notRD) during Read operations and transfers serial data to the
Write Data output during write operations.
Data Register - This 8-bit register is used as a holding register during Disk
read and Write operations. In Disk Read operations the assembled data byte is
transferred in parallel to the Data register from the Data Shift Register. In
Disk Write operations information is transferred in parallel from the the
Data Register to the Data Shift Register.
When executing the Seek command the Data Register holds the address of the
desired Track position. This register is loaded from the DAL and gated into
the DAL under processor control.
Track Register - This 8-bit register holds the track number of the current
Read/Write hed position. It is incremented by one every time the head is
stepped in and decremented by one when the head is stepped out (towards track
00). The contents of the register are compared with the recorded track number
in the ID field during disk Read, Write and Verify operations. The track
register can be loaded from or transferred to the DAL. This register should
not be loaded when the device is busy.
Sector Register (SR) - This 8-bit register holds address of the desired
sector postition. The contents of the register are compared with the recorded
sector number in the ID field during disk Read or Write operations. The
Sector Register contents can be loaded from or transferred to the DAL. This
register should not be loaded when the device is busy.
Command Register (CR) - This 8-bit register holds the command presently being
executed. This register should not be loaded when the device is busy unless
the new command is a force interrupt. The command register can be loaded from
the DAL, but not read into the DAL.
Status Register (STR) - This 8-bit register holds device Status information.
The meaning of the status bits is a function of the type of command
previously executed. This register can be read into the DAL, but not loaded
from the DAL.
CRC Logic - This logic is used to check or to generate the 16-bit Cyclic
Redundancy Check (CRC). The polynominal is: g(x)=x^16+x^12+x^5+1 The CRC
includes all information starting with the address mark and up to the CRC
characters. The CRC register is preset to ones prior to data being shifted
through the circuit.
Arithmetic/Logic Unit (ALU) - The ALU is a serial comperator, incrementer and
decrementer and is used for register modification and comparisons with the
disk recorded ID field.
Timing and Control - All computer and floppy disk interface controls are
generated through this logic. The internal device timing is generated from an
external crystal clock. The FD1770 has two different modes of operation
according to the state of notDDEN. When notDDEN = 0., double density is
enabled. When notDDEN = 1, single density is enabled.
AM Detector - The address mark detector detects ID, data and index address
marks during read and write operations.
Data Separator - A digital data separator consisting of a nng shift register
and data window detection logic provides read data and a recovery clock to
the AM detector.
PROCESSOR INTERFACE
The interface to the processor is accomplished through the eight Data Access
Lines (DAL) and associated control signals. The DAL are used to transfer
data, Status and Control words out of, or into the WD1770. The DAL are three
state buffers that are enabled as output drivers when Chip Select (notCS) and
R/notW = 1 are active or act as input receivers when notCS and R/notW = 0 are
active.
When transfer of data with the Floppy Disk Controller is required by the host
processor, the device address is decoded and notCS is made low. The address
bits A1 and A0, combined with the signal R/notW during a Read operation or
Write operation are interpreted as selecing the following registers:
+----+----+-----------------+------------------+
! A1 ! A0 ! READ ! WRITE !
+----+----+-----------------+------------------+
! 0 ! 0 ! Status Register ! Command Register !
! 0 ! 1 ! Track register ! Track Register !
! 1 ! 0 ! Sector register ! Sector Register !
! 1 ! 1 ! Data Register ! Data Register !
+----+----+-----------------+------------------+
During Direct Memory Access (DMA) types of data transfers between the Data
Register of the WD1770 and the processor, the Data ReQuest (DRQ) output is
used in Data Transfer control. This signal also appears as status bit 1
during Read and Write operations.
On Disk Read operations the Data Request is activated (set high) when an
assembled serial input byte is transferred in parallel to the Data Register.
This bit is cleared when the Data Register is read by the processor. If the
Data Register is read after one or more characters are lost, by having new
data transferred to the register prior to processor readout, the Lost Data
bit is set in the Status Register. The read operation continues until the end
of sector is reached.
On Disk Write operations the Data ReQuest is activated when the Data
Registers its contents to the Data Shift Register and requires a new data
byte. It is reset when the Data Register is loaded with new data by the
processor. If new data is not loaded at the time serial byte is required by
the Floppy Disk, a byte of zeroes is written on the diskette and the Lost
Data bit is set in the Status Register.
At the completion of every command an INTRQ is generated. INTRQ is reset by
either reading the status register or by loading the command register with a
new command. In addition INTRQ is generated if a Force Interrupt command
condition is met.
The WD1770 has two modes of operation according to the state of notDDEN (pin
26). When notDDEN = 1, single density is selected. In either case, the CLK
input (pin 18) is at 8 MHz.
GENERAL DISK READ OPERATIONS
Sector lengths of 128, 256, 512 or 1024 bytes are obtainable in either FM or
MFM formats. For FM formats, notDDEN should be placed to logical "1". For MFM
formats, notDDEN should be placed to logic "0". Sector lengths are determined
at format time by hte fourth byte in the ID field.
+---------------------------------+
! SECTOR LENGTH TABLE !
+---------------+-----------------+
! SECTOR LENGTH ! NUMBER OF BYTES !
! FIELD (HEX) ! IN SECTOR (DEC) !
+---------------+-----------------+
! 00 ! 128 !
! 01 ! 256 !
! 02 ! 512 !
! 03 ! 1024 !
+---------------+-----------------+
The number of sectors per track as far as the WD1770 is concerned can be from
1 to 255 sectors. The number of tracks as far as the WD1770 is concerned is
from 0 to 255 tracks.
GENERAL DISK WRITE OPERATION
When writing is to take place on the diskette, the Write Gate (WG) output is
activated, allowing current to flow into the Read/Write head. As a precaution
to erroneous writing the first data must be loaded into the Data Register in
response to a Data ReQuest from the device before the Write Gate signal can
be activated.
Writing is inhibited when the notWP (Write Protect) input is a logic low, in
which case any Write command is immediately terminated, an interrupt
generated and the Write Protection status bit is set.
For Write operations, the WD1770 provides Write Gate (pin 21) to enable a
write condition and Write Data (pin 22) which consists of a series of active
high pulses. These pulses contain both Clock and Data information in FM or
MFM. Write Data provides the unique missing clock patterns for recording
Address Marks.
The Precomp Enable bit in Write commands allow automatic Write
Precompensation to take place. The outgoing Write Data Stream is delayed or
advanced according to the following table:
+----------+--------+------+
! PATTERN ! MFM ! FM !
+----------+--------+------+
! x 1 1 0 ! Early ! N/A !
! x 0 1 1 ! Late ! N/A !
! 0 0 0 1 ! Early ! N/A !
! 1 0 0 0 ! Late ! N/A !
+----------+--------+------+
^ ^ ^ ^
! ! ! +- Next bit to be sent
! ! +--- Current bit sending
+-+----- Previous bits sent
Precompensation is typically enabled on the innermost tracks where bit shifts
usually occur and bit density is at its maximum.
COMMAND DESCRIPTION
De WD1770 will accept eleven commands. Command words should only be loaded in
the Command Register when the Busy status bit is off (Status bit 0). The one
exception is the force interrupt command. Whenever a command is being
executed, the Busy status bit is set. When a command is completed, an
interrupt is generated and the Busy status bit is reset. The status register
indicates whether the completed command encountered an error or was fault
free. For ease of discussion, commands are divided into four types. Commands
and types are summarized in tale 1.
COMMAND SUMMARY
+------+----------+-------------------------+
! ! ! BITS !
! TYPE ! COMMAND ! 7 6 5 4 3 2 1 0 !
+------+----------+-------------------------+
! 1 ! Restore ! 0 0 0 0 h v r1 r0 !
! 1 ! Seek ! 0 0 0 1 h v r1 r0 !
! 1 ! Step ! 0 0 1 u h v r1 r0 !
! 1 ! Step-in ! 0 1 0 u h v r1 r0 !
! 1 ! Step-out ! 0 1 1 u h v r1 r0 !
! 2 ! Rd sectr ! 1 0 0 m h E 0 0 !
! 2 ! Wt sectr ! 1 0 1 m h E P a0 !
! 3 ! Rd addr ! 1 1 0 0 h E 0 0 !
! 3 ! Rd track ! 1 1 1 0 h E 0 0 !
! 3 ! Wt track ! 1 1 1 1 h E P 0 !
! 4 ! Forc int ! 1 1 0 1 i3 i2 i1 i0 !
+------+----------+-------------------------+
FLAG SUMMARY
+-------------------------------------------+
! TYPE 1 COMMANDS !
+-------------------------------------------+
! h = Motor on Flag (bit 3) !
! h = 0 Enable spin-up Sequence !
! h = 1 Disable spin-up Sequemce !
! !
! v = Verify Flag (bit 2) !
! v = 0 No verify !
! v = 1 Verify on destn track !
! !
! r1, r0 = Stepping rate (bits 1, 0) !
! r1 r0 WD1770 WD1772 !
! 0 0 6 ms 2 ms !
! 0 1 12 ms 3 ms !
! 1 0 20 ms 5 ms !
! 1 1 30 ms 6 ms !
! !
! u = Update Flag (bit 4) !
! u = 0 No update !
! u = 1 Update Track Register !
+-------------------------------------------+
+-------------------------------------------+
! TYPE 2 & 3 COMMANDS !
+-------------------------------------------+
! m = Multiple Sector Flag (bit 4) !
! m = 0 Single sector !
! m = 1 Multiple sector !
! !
! a0= Data Address Mark (bit 0) !
! a0= 0 Write normal Data Mark !
! a0= 1 Write Deleted Data Mark !
! !
! E = 30ms Settling Delay (bit 2) !
! E = 0 No delay !
! E = 1 Add 30ms Delay !
! !
! P = Write Precompensation (bit 1) !
! P = 0 Enable Write Precomp !
! P = 1 Disable Write Precomp !
+-------------------------------------------+
+-------------------------------------------+
! TYPE 4 COMMANDS !
+-------------------------------------------+
! i3-i0 Interrupt condition (bit 3-0) !
! i0= 1 Don't care !
! i1= 1 Don't care !
! i2= 1 Interrupt on index pulse !
! i3= 1 Immediate interrupt !
! 13-i0 = 0 Terminate without interrupt !
+-------------------------------------------+
TYPE 1 COMMANDS
The type 1 commands include the Restore, Seek, Step, Step-in and Step-out
commands. Each of the Type 1 commands contains a rate field (r0, r1), which
determines the stepping motor rate.
A 4uS (MFM) of 8uS (FM) pulse is provided as an output to the drive. For
every step pulse issued, the drive moves one track location in a direction
determined by the direction output. The chip will step the drive in the same
direction it last stepped, unless the command changes the direction.
The direction signal is active high when stepping in and low when stepping
out. The Direction signal is valid 24uS before the first stepping pulse is
generated.
After the last directional step an additional 30 milliseconds of head
settling time takes if the verify flag is set in type 1 commands. There is
also a 30mS head settling time if the E flag is set in any Type 2 or 3
command.
When a Seek, Step or Restore command is executed, an optional verification of
Read/Write head position can be performed by setting bit 2 (V=1) in the
command word to a logic "1". The verification operation begins at the end of
the 30 millisecond settling time after the head is loaded against the media.
The track number from the first encountered ID field is compared against the
contents of the Track Register. If the track numbers compare and the ID field
CRC is correct, the verify operations is complete and an INTRQ is generated
with no errors. If there is a match but not a valid CRC, the CRC error status
bit is set (Status bit 3) and the next encountered ID field is read from the
disk for the verification operation.
The WD1770 must find an ID field with correct track number and correct CRC
within 5 revolutions of the media, otherwise the seek error is set and an
INTRQ is generated. If V=0 no verification is performed.
All commands except the Force Interrupt command may be programmed via the h
Flag to delay for spindle motor startup time. If the h Flag is set and the
Motor On line (pin 20) is low when a command is received, the WD1770 will
force Motor On to a logic "1" and wait 6 revolutions before executing the
command. At 300rpm this guarantees a one second spindle startup time. If
after finishing the command, the device remains idle for 10 revolutions, the
Motor On line will go back to a logic "0". If a command is issued while Motor
On is high, the command will execute immediately, defeating the 6 revolutions
start up. This feature allows consecutive Read or Write commands without
waiting for motor start up each time; the WD1770 assumes the spindle motor is
up to speed.
RESTORE (SEEK TRACK 0)
Upon receipt of this command, the Track 00 (notTR00) input is sampled. If
notTR00 is active low indicating the Read/Write head is positioned over track
0, the Track register is loaded with zeroes and an interrupt is generated. If
notTR00 is not active low, stepping pulses (pin 16) at a rate specified by
the r1, r0 field are issued until the notTR00 input is activated. At this
time, the Track Register is loaded with zeroes and an interrupt is generated.
If the notTR00 input does not go active low after 255 stepping pulses, the
WD1770 terminates operation, interrupts and sets the Seek error status bit,
providing the V flag is set. A verification als takes place if the V flag is
set. The h bit allows the Motor On option at the start of command.
SEEK
This command assumes that the track register contains the track number of the
current position of the Read/Write head and the Data Register contains the
desired track number. The WD1770 will update the Track Register and issue
stepping pulses in the appropiate direction until the contents of the Track
Register are equal to the contents of the Data Register (the desired Track
location). A verification operation takes place if the V flag is on. The h
bit allows the Motor On option at the start of the command. An interrupt is
generated at the completion of the command. Note: When using mutiple drives,
the track register must be updated for the drive selected before seeks are
issued.
STEP
Upon receipt of this command, the WD1770 issues one stepping pulse to the
disk drive. The stepping motor direction is the same as in the previous step
command. After a delay determined by the r1, r0 field, a verification takes
place if the V flag is on. If the U flag is on, the Track Register is
updated. The h bit allows the Motor On option at the start of the command. An
interrupt is generated at the completion of the command.
STEP-IN
Upon receipt of this command, the WD1770 issues one stepping pulse in the
direction towards track 76. If the U flag is on, the Track Register is
incremented by one. After a delay determined by the r1, r0 field, a
verification takes place if the V flag is on. The h bit alows the Motor On
option at the startof the command. An interrupt is generated at the
completion of the command
STEP-IN
Upon receipt of this command, the WD1770 issues one stepping pulse in the
direction towards track 0. If the U flag is on, the Track Register is
decremented by one. After delay determined by the r1, r0 field, a
verification takes place if the V flag is on. The h bit allows the Motor On
option at the start of the command.
TYPE 2 COMMANDS
The type 2 commands are the read sector and write sector commands. Prior to
loading the type 2 command into the command register, the computer must load
the sector register with the desired sector number. Upon receipt of the type
2 command, the busy status bit is set. If the E flag is 1, the command will
execute after 30ms delay.
When an ID field is located on the disk, the WD1770 compares the track number
on the ID field with the Track register. If there is not a match, the next
encountered ID field is read and a comparison is again made. If there was a
match, the Sector Number of the ID field is compared with the Sector
Register. If there is not a Sector match, the next encountered ID field is
read off the disk and comparisons again made. If the ID field CRC is correct,
the data field is then located and will be either written into, or read from
depending upon the command. The WD1770 must find an ID field with a track
number, sector number and CRC within four revolutions of the disk, otherwise,
the Record not found status bit is set (status bit 4) and the command is
terminated with an interrupt (INTRQ).
Each of the type 2 commands contains an (m) flag which determines if multiple
records (sectors) are to be read or written, depending upon the command. If
m=0, a single record is read or written and an interrupt is generated at the
completion of the command. If m=1, multiple records are read or written with
the sector register internally updated so that an address verification can
occur on the next record. The WD1770 will continue to read or write multiple
records and update the sector register in numerical ascending sequence until
the sector number exceeds the number of sectors on the track or until the
Force Interrupt command is loaded in the command register, which terminates
the command and generates an interrupt.
For example: If the WD1770 is instructed to read sector 27 and there are
only 26 sectors on the track, the sector register exceeds
the number available. The WD1770 will search for 5 disk
revolutions, interrupt out, reset busy and set the record
not found status bit.
READ SECTOR
Upon receipt of the Read Sector command, the busy status bit is set, and when
an ID field is encountered that has the correct track number, corect sector
number and correct CRC, the data field is presented to the computer. The data
address mark of the data field must be found within 30 bytes in single
density and 43 bytes in double density of the last ID field CRC byte; if not,
the ID field is searched for and verified again followed by the Data Address
Mark search. If after 5 revolutions the DAM cannot be found, the record not
found bit is set and the operation terminated. When the first character or
byte of the data field has been shifted through the DSR, it is transferred to
the DR, and DRQ is generated. When the next byte is accumulated in the DSR,
it is transferred to the DR and another DRQ is generated. If the computer has
not read the previous contents of the DR before a new character is
transferred that character will be lost and the lost data status bit is set.
This sequence continues until the complete data field has been inputted to
the computer. If there is a CRC error at the end of the data field, the CRC
error status bit is set and the command is terminated (even if it is a
multiple record command).
At the end of the Read operation, the type of Data Address Mark encountered
in the data field is recorded in the status register (bit 5) as shown:
+---------------------+
! STATUS BIT 5 !
+---------------------+
! 1 Deleted Data Mark !
! 0 Data Mark !
+---------------------+
WRITE SECTOR
Upon receipt of the Write Sector command, the Busy status bit is set. When an
ID field is encountered that has the correct track number, correct sector
number and correct CRC, a DRQ is generated. The WD1770 counts off 11 bytes in
single density and 22 bytes in double density from the CRC field and the
Write Gate (WG) output is made active if the DRQ is serviced (i.e. the DR has
been loaded by the computer). If DRQ has not been serviced, the command is
terminated and the lost data status bit is set. If the DRQ has been serviced,
the WG is made active and six bytes of zeroes in single density and 12 bytes
in double density are then written to the disk. At this time, the Data
Address Mark is then written on the disk as determined by the a0 field of the
command as shown below:
+-----+---------------------------+
! a0 ! DATA ADDRESS MARK (BIT 0) !
+-----+---------------------------+
! 1 ! Deleted Data Mark !
! 0 ! Data Mark !
+-----+---------------------------+
The WD1770 then writes the data field and generates DRQ's to the computer. If
the DRQ is not serviced in time for conitinious writing the lost data status
bit is set and a byte of zeroes is written on the disk. The command is not
terminated. After the last data byte has been written on the disk, the two
byte CRC is computed internally and written on the disk followed by one byte
of logic ones in FM or MFM. The WG output is then activated. INTRQ will set
24uSec (MFM) after the last CRC byte is written. For partial sector writing,
the proper method is to write data and fill the balance with zeroes.
TYPE 3 COMMANDS
READ ADDRESS
Upon receipt of the Read Address command, the Busy status bit is set. The
next encountered ID field is then read in from the disk, and six data bytes
of the ID field are assembled and transferred to the DR, and a DRQ is
generated for each byte. The six bytes of the ID field are shown below.
+-------+--------+--------+--------+-----+-----+
! TRACK ! SIDE ! SECTOR ! SECTOR ! CRC ! CRC !
! ADDR ! NUMBER ! ADDR ! LENGTH ! 1 ! 2 !
+-------+--------+--------+--------+-----+-----+
! 1 ! 2 ! 3 ! 4 ! 5 ! 6 !
+-------+--------+--------+--------+-----+-----+
Although the CRC characters are transferred to the computer, the WD1770
checks for validity and the CRC error status bit if there is a CRC error. The
Track Address of the ID field is written into the sector register so that a
comparison can be made by the user. At the end of the operation an interrupt
is generated and the Busy status bit is reset.
READ TRACK
Upon receipt of the Read Track command, the head is loaded and the Busy
status bit is set. Reading starts with the leading edge of the first
encountered index pulse and continues until the next index pulse. All gap,
Header and data bytes are assembled and transferred to the data register and
DRQ's are generated for each byte. The accumulation of bytes is synchronized
to each address mark encountered. An interrupt is generated at the completion
of the command. This command has several characteristics which makes it
suitable for diagnostic purposes. They are: no CRC checking is performed; gap
information is included in the datastream; and the address mark detector is
on for the duration of the command. Because the AM detector is always on,
write splices or noise may cause the chip to look for an DM.
The ID am, ID field, ID CRC bytes, DAM, data, and data CRC bytes for each
sector will be correct. The Gap Bytes may be read incorrectly during
write-splice time because of synchronization.
WRITE TRACK FORMATTING THE DISK
(Refer to section type 3 command for flow diagrams).
Formatting the disk is a relatively simple task when operating programmed I/O
or when operating under DMA with a large amount of memory. Data and gap
information must be provided at the computer interface. Formatting the disk
is accomplished by positioning the R/W head over the desired track and
issuing the Write Track command.
Upon receipt of the Write Track command, the Busy status bit is set. Writing
starts with the leading edge of the first encountered index pulse and
continues until the next index pulse, at which time the interrupt is
activated. The Data ReQuest is activated immediately upon receiving the
command, but writing will not start until after the first byte has been
loaded into the Data Register. If the DR has not been loaded within 3 byte
times, the operation is terminated making the device not busy, the Lost Data
Status bit is set, and the interrupt is activated. If a byte is not present
in the DR when needed, a byte of zeroes is substituted.
This sequence continues from one index mark to the next index mark. Normally,
whatever data pattern appears in the data register is written on the disk
with a normal clock pattern. However, if the WD1770 detects a data pattern of
F5 through FE in the data register, this is interpreted as data address marks
with missing clocks or CRC generation.
+--------------+-----------------------------+--------------------------+
! DATA PATTERN ! ! !
! IN DR (HEX) ! IN FM (not DDEN = 1) ! In MFM (notDDEN = 0) !
+--------------+-----------------------------+--------------------------+
! 00 thru F4 ! Wt 00 thru F4 with CLK = FF ! Wt 00 thru F4 in MFM !
! F5 ! Not Allowed ! Wt A1 in MFM, Preset CRC !
! F6 ! Not Allowed ! Wt C2 in MFM !
! F7 ! Generate 2 CRC bytes ! Generate 2 CRC bytes !
! F8 thru FB ! Wt F8-FB, Clk=C7,Preset CRC ! Wt F8 thru Fb, in MFM !
! FC ! Wt FC with Clk=D7 ! Wt FC in MFM !
! FD ! Wt FD with Clk=FF ! Wt FD in MFM !
! FE ! Wt FE, Clk=C7, Preset CRC ! Wt FE in MFM !
! FF ! Wt FF with Clk=FF ! Wt FF in MFM !
+--------------+-----------------------------+--------------------------+
The CRC generator is initialized when any data byte from F8 to FE is about to
be transferred from the DR to the DSR in FM or by receipt of F5 in MFM. An F7
pattern will generate two CRC characters in FM or MFM. As a consequence, the
patterns F5 through FE must not appear in the gaps, data fields or ID fields.
Also, CRC's must be generated by an F7 pattern.
Disks may be formatted in IBM 3740 or system 34 formats with sector lengths
of 128, 256, 512 or 1024 bytes.
TYPE 4 COMMANDS
The forced interrupt command is generally used to terminate a multiple sector
read or write command or to insure Type 1 status in the status register. This
command can be loaded into the command register at any time. If there is a
current command under execution (Busy status bit set) the command will be
terminated and the busy status bit reset.
The lower four bits of the command determine the conditional interrupt as
follows:
i0 = Don't care
i1 = Don't care
i2 = Every index puls
i3 = Immediate interrupt
The conditional interrupt is enabled when bit positions of the command
(i3-i0) are set to a "1". Then, when the condition for interrupt is met, the
INTRQ line will go high signifying that the condition specified has occurred.
If i3-i0 are all set to zero (HEX D0), no interrupt will occur, but any
command presently under execution will be immediately terminated. When using
the immediate interrupt condition (i3=1) an interrupt will be immediately
generated and the current command terminated. Reading the status or writing
to the command register will not automatically clear the interrupt. The HEX
D0 is the only command that will enable the immediate interrupt (HEX D6) to
clear on a subsequent load command register or read status register
operation. Follow a HEX D6 with D0 command.
Wait 16uSec (double density) or 32uSec (single density) before issuing a new
command after issuing the forced interrupt. Loading a new command sooner than
this will nullify the forced interrupt.
Forced interrupt stops any command at the end of an internal
micro-instruction and generates INTRQ when the specified condition is met.
Forced interrupt will wait until ALU operations in progress are complete (CRC
calculations, compares, etc.).
STATUS REGISTER
Upon receipt of any command, except the Force interrupt command the Busy
status bit is set and the rest of the status bits are updated or cleared for
the new command. If the Force Interrupt Command is received when there is a
current command under execution, the Busy status bit is reset and the rest of
the status bits are unchanged. If the Forced interrupt command is received
when there is not a current command under execution, the Busy status bit is
reset and the rest of the status bits are updated or cleared. In this case,
Status reflects the type 1 commands.
The user has the option of reading the status register through program
control or using the DRQ with DMA or interrupt methods. When the Data
register is read the DRQ bit in the status register and the DRQ line are
automatically reset. A write to the Data Register also causes both DRQ's to
reset.
The busy bit is the status may be monitored with a user program to determine
when a command is complete, in lieu of using the INTRQ line. When using the
INTRQ, a busy status check is not recommended because a read of the status
register to determine the condition of busy will reset the INTRQ line.
The format of the Status register is shown below:
+---------------------------------------+
! (BITS) !
! 7 6 5 4 3 2 1 0 !
+----+----+----+----+----+----+----+----+
! s7 ! s6 ! s5 ! s4 ! s3 ! s2 ! s1 ! s0 !
+----+----+----+----+----+----+----+----+
RECOMMENDED - 128 BYTES/SECTOR
Shown below is the recommended single-density format with 128 bytes/sector.
In order to format a diskette, the user must issue the Write Track command
and load the data register with the following values. For every byte to be
written there is one Data Request.
+----------+------------------------------+
! NUMBER ! !
! OF BYTES ! HEX VALUE OF BYTE WRITTEN !
+----------+------------------------------+
! 40 ! FF (or 00) !
! +---- 1) ! !
! ! 6 ! 00 !
! ! 1 ! FE (ID field Address Mark) !
! ! 1 ! .. Track number !
! ! 1 ! .. Side number (0 or 1) !
! ! 1 ! .. Sector number (1 thru 1A) !
! ! 1 ! 00 (Sector length) !
! ! 1 ! F7 (2 CRC's written) !
! ! 11 ! FF (or 00) !
! ! 6 ! 00 !
! ! 1 ! FB (Data Address Mark) !
! ! 128 ! .. Data (IBM uses E5) !
! ! 1 ! F7 (2 CRC's written) !
! ! 10 ! FF (or 00) !
! +---- ! !
! 369 2) ! FF (or 00) !
+----------+------------------------------+
1) Write bracketed field 16 times.
2) Continue writing until WD1770 interrupts out, approx. 369 bytes.
256 BYTES/SECTOR
Shown below is the recommended dual-density format with 256 bytes/sector. In
order to format a diskette the user must issue the Write Track command and
load the data register with the following values. For every byte to be
written there is one data request.
+----------+------------------------------+
! NUMBER ! !
! OF BYTES ! HEX VALUE OF BYTE WRITTEN !
+----------+------------------------------+
! 60 ! 4E !
! +---- 1) ! !
! ! 12 ! 00 !
! ! 3 ! F5 (Writes A1) !
! ! 1 ! FE (ID field Address Mark) !
! ! 1 ! .. Track number (0 thru 4C) !
! ! 1 ! .. Side number (0 or 1) !
! ! 1 ! .. Sector number (1 thru 1A) !
! ! 1 ! 01 (Sector length) !
! ! 1 ! F7 (2 CRC's written) !
! ! 22 ! 4E !
! ! 12 ! 00 !
! ! 3 ! F5 (Writes A1) !
! ! 1 ! FB (Data Address Mark) !
! ! 256 ! .. Data !
! ! 1 ! F7 (2 CRC's written) !
! ! 24 ! 4E !
! +---- ! !
! 668 2) ! 4E !
+----------+------------------------------+
1) Write bracketed field 16 times.
2) Continue writing until WD1770 interrupts out, approx. 668 bytes.
NON-STANDARD FORMATS
Variations in the recommended formats are possible to a limited extent if the
following requirements are met.
1) Sector length must be 128, 256, 512 or 1024 bytes.
2) Gap 2 cannot be varied from the recommended format.
3) 3 bytes of A1 must be used in MFM.
In addition, the index Address Mark is not required for operation by the
WD1770. Gap 1, 3 and 4 lengths can be as short as 2 bytes for WD1770
operation, however PLL lock up time, motor speed variation, write splice
area, etc. will add more bytes to each gap to achieve proper operation. It is
recommended that the recommended format be used for highest system
reliability.
+----------+-------------+-------------+
! ! ! !
+----------+-------------+-------------+
! Gap 1 ! 16 bytes FF ! 32 bytes 4E !
! ! ! !
! Gap 2 ! 11 bytes FF ! 22 bytes 4E !
! ! ! !
! 1) ! 6 bytes 00 ! 12 bytes 00 !
! 1) ! ! 3 bytes A1 !
! ! ! !
! Gap 3 2) ! 10 bytes FF ! 24 bytes 4E !
! ! 4 bytes 00 ! 8 bytes 00 !
! ! ! 3 bytes A1 !
! ! ! !
! Gap 4 ! 16 bytes FF ! 16 bytes 4E !
+----------+-------------+-------------+
1) Byte counts must be exact
2) Byte counts are minimum, except exactly 3 bytes of A1 must
be written.
STATUS REGISTER DESCRIPTION
+-----+---------------+-------------------------------------------------+
! BIT ! NAME ! MEANING !
+-----+---------------+-------------------------------------------------+
! s7 ! MOTOR ON ! This bit reflects the status of the Motor On !
! ! ! output !
+-----+---------------+-------------------------------------------------+
! s6 ! WRITE PROTECT ! On read record: not used. On read track: not !
! ! ! used. On any write: it indicates a Write !
! ! ! Protect. This bit is reset when updated. !
+-----+---------------+-------------------------------------------------+
! s5 ! RECORD TYPE ! When set, this bit indicates that the Motor !
! ! SPIN-UP ! Spin-Up sequence has completed (6 revolutions) !
! ! ! on type 1 commands. Type 2 & 3 commands, this !
! ! ! bit indicates record Type. 0 = Data Mark, 1 = !
! ! ! Deleted Data Mark. !
+-----+---------------+-------------------------------------------------+
! s4 ! RECORD NOT ! When set, it indicates that the desired track, !
! ! FOUND (RNF) ! sector, or side were not found. This bit is !
! ! ! reset when updated. !
+-----+---------------+-------------------------------------------------+
! s3 ! CRC ERROR ! If s4 is set, an error is found in one or more !
! ! ! ID fields; otherwise it indicates error in data !
! ! ! field. This bit is reset when updated. !
+-----+---------------+-------------------------------------------------+
! s2 ! LOST DATA/ ! When set, it indicates the computer did not !
! ! TRACK 00 ! respond to DRQ in one byte time. This bit is !
! ! ! reset to zero when update. On type 1 commands, !
! ! ! this bit reflects the status of the TRACK 00 !
! ! ! pin. !
+-----+---------------+-------------------------------------------------+
! s1 ! DATA REQUEST/ ! This bit is a copy of the DRQ output. When set, !
! ! INDEX ! it indicates the DR is full on a Read Operation !
! ! ! or the DR is empty on a write operation. This !
! ! ! bit is reset to zero when updated. On type 1 !
! ! ! commands, this bit indicates the status of the !
! ! ! index pin. !
+-----+---------------+-------------------------------------------------+
! s0 ! BUSY ! When set, command is under execution. When !
! ! ! reset, no command is under execution. !
+-----+---------------+-------------------------------------------------+
TYPE 1 COMMAND FLOW
!
!
!-------<--------+
! !
+------+------+ !
/ has a type 1 \ no !
! command been !----->-+
\ /
+------+------+
!yes
+-----------+-----------+
! set busy, reset drq, !
! seek err, drq, intrq !
+-----------+-----------+
!
+--+--+
/ is \ no
! h = 0 !-------->-------+
\ ? / !
+--+--+ !
!yes !
+--------------+--------------+ !
! set MO, wait 6 index pulses ! !
+--------------+--------------+ !
! !
!-------<-------------+
!
+---+---+
/ is \ yes +-----------+
! command a !---->----! set !->-+
\step-in ?/ ! direction ! !
+---+---+ +-----------+ !
!no !
+----+----+ !
/ is \ yes +-----------+ !
! command a !--->----! reset !->-+
\ stepout ? / ! direction ! !
+----+----+ +-----------+ !
!no !
+---+---+ !
/ is \ yes !
! command a !----------------------->-+
\ step ? / !
+---+---+ !
!no !
+---+---+ +--+--+
/ is \ yes yes / is \
! command a !-----+ +-<---! u = 1 !
\ seek / ! ! \ ? /
+---+---+ ! ! +--+--+
restore !no ! ! !no
+-----+-----+ ! ! !
! FF to TR ! ! ! !
+-----+-----+ ! ! !
! ! ! !
+-----+-----+ ! ! !
! 0 to DR !-<---+ ! !
+-----+-----+ ! !
! ! !
+-+-+ +-+-+ +-+-+
! A ! ! B ! ! C !
\ / \ / \ /
+---+
! A !
\ /
!
+----------->---!
! !
! +-----+-----+
! ! DR to DSR !
! +-----+-----+
! !
! +--+--+
! / is \ yes
! ! TR =DSR !------------------->--------+
! \ ? / !
! +--+--+ !
! !no !
! +--+--+ !
! / is \ yes !
! ! DSR< TR !--------->----+ !
! +---+ \ ? / ! !
! ! B ! +--+--+ ! !
! \ / !no ! !
! ! +--------+--------+ +-------+-------+ !
! ! ! reset direction ! ! set direction ! !
! ! +--------+--------+ +-------+-------+ !
! ! ! ! !
! +------>----+------<------------+ !
! ! !
! +---+---+ !
! / is \ yes !
! ! direction !------>--+ !
! +---+ \ = 1 ? / ! !
! ! C ! +---+---+ ! !
! \ / !no ! !
! ! +----+----+ +----+----+ !
! ! ! inc TR ! ! dec TR ! !
! ! +----+----+ +----+----+ !
! ! ! ! !
! +------>----+-----<---------+ !
! ! !
! +----+----+ !
! / is head at\ yes +---------+ !
! ! track 0 and !--->-! 0 to TR !------->--+
! ! direction ! +---------+ !
! \ is 0 ? / !
! +----+----+ !
! !no !
! +-----------+-----------+ !
! ! issue one step pulse ! !
! +-----------+-----------+ !
! ! !
! +-----------+-----------+ !
! ! delay acc. to r1, r0 ! !
! +-----------+-----------+ !
! ! !
! +------+------+ !
! no / is command a \ yes !
+-<----! step, step-in !--------->-----+----<---+
\ or step-out ? / !
+-------------+ +-+-+
! D !
\ /
+---+
! D !
\ /
!
+-+-+
/ is \ no
! V = 1 !----->-----+
\ ? / !
+-+-+ /------+------\
!yes ! intrq, reset !
+------------->------------+ ! busy status !
! ! \-------------/
! +----+----+
! / have 6 \ yes
! ! index holes !------>--+
! \ passed ? / !
! +----+----+ /------+-------\
! !no ! intrq, reset !
! +----+----+ ! busy, set seek !
! no / has ID \ ! error !
+----<--------------! am been ! \--------------/
! \ detected /
! +----+----+
! !yes
! +----+----+
! no / does TR = \
+----<--------------! track nr of !
! \ ID field /
! +----+----+
! !yes
! +-------+ +----+----+
! ! SET ! yes / is there \
+-<---! CRC !-<---! a crc !
! ERROR ! \ CRC error /
+-------+ +----+----+
!no
+-----+-----+
! reset CRC !
+-----+-----+
!
/----+-----\
! intrq, !
! reset busy !
\----------/
TYPE 2
!
!
+---<-------+
! !
+---+---+ !
/ is type \ no !
! 2 command !--->-+
\ received/
+---+---+
!yes
+--------------+--------------+
! set busy, reset drq, !
! lost data, record not found !
! status bit 5 & 6 intrq !
+--------------+--------------+
!
+-+-+
no / is \
+--------<-----! h = 1 !
! \ ? /
! +-+-+
! !yes
! +--------+--------+
! ! set MO, wait !
! ! 6 index pulses !
! +--------+--------+
! !
+------------->----+
!
+-+-+
/ is \ no
! E = 1 !--->-+
\ ? / !
+-+-+ !
!yes !
+------>----+ !
! ! !
! +---+---+ !
! no / has \ !
+---+ +-<---! 30 mS ! !
! 4 ! \ expired / !
\ / +---+---+ !
! !yes !
+------------->----+----<----+
!
+---+---+
yes / is \
+----<-------! command !
! \ a write /
+--+--+ +---+---+
/ is \ !no
yes ! write ! no !
+---<----! protect !---------->--+
! \ on ? / !
! +--+--+ +-+-+
! ! 1 !
! /-----------------\ \ /
+---->-! intrq, reset busy !
! set write protect !
\-----------------/
+-+-+
! 1 !
\ /
!
+---------------------->---------+
! !
! +----+----+
! / have 5 \ yes
! ! index holes !--------->-----+
! \ passed ? / !
! +----+----+ /----------+----------\
! !no ! intrq, reset busy !
! +-----+-----+ ! set record not found !
! no / has ID am \ \---------------------/
+------<-----------------! been !
! \ detected ? /
! +-----+-----+
! !yes
! +-----+-----+
! no / does TR = \
+------<-----------------! track address !
! \ of ID field /
! +-----+-----+
! !yes
! +-----+-----+
! no / does SR = \
+-------<----------------! sector addr !
! \ of ID field /
! +-----+-----+
! !yes
! +------------+------------+
! ! bring in sector length !
! ! field, store in !
! ! internal register !
! +------------+------------+
! !
! +---+---+
! +--------------+ yes / is there\ no
+-<---! set CRC !-<---! a crc !----->--+
! status error ! \ error ? / !
+--------------+ +---+---+ +-----+-----+
! reset CRC !
+-----+-----+
!
+---+---+
yes / is \
+--<-----! command a !
! \ write ? /
! +---+---+
! !no
+-+-+ +-+-+
! 3 ! ! 2 ! read
\ / \ /
+-+-+ read sector
! 2 ! sequence
\ /
!
+----+----+
/ has data \ no
! AM occurred !---------->-------+
\ in time ? / !
+----+----+ !
!yes !
+----------+----------+ +-+-+
! put recording type ! ! 1 !
! in status reg bit 3 ! \ /
+----------+----------+
!
+-----<-------+
! !
+---+---+ !
/has first\ no !
! byte been !---->--+
! assembled !
\ in DSR ?/
+---+---+
!yes
+------>-----+
! !
! +----+----+
! ! set DRQ !
! +----+----+
! !
! +-----<-------+
! ! !
! +---+---+ !
! / has next\ no !
! ! byte been !---->--+
! ! assembled !
! \ in DSR ?/
! +---+---+
! !yes
! +----+----+
! / has DR \ no +--------+--------+
! ! been read !---->-! set data lost !
! \ DR = 0 ? / +--------+--------+
! +----+----+ !
! !yes !
! +-------<--------------+
! !
! +----+----+ +---+
! no / have all \ ! 5 !
+-<---! bytes been ! \ /
\ inputted / !
+----+----+ +------>--+
!yes ! !
+-+-+ ! +-+-+
/ CRC \ no ! / is \ no
! error !---->-+ ! M = 1 !---------->----+
\ ? / \ ? / !
+-+-+ +-+-+ !
!yes !yes !
! +------+------+ !
/------+------\ ! inc sectreg ! !
! intrq, reset ! +------+------+ !
! busy, set crc ! ! !
! error ! +-+-+ /--------+--------\
\-------------/ ! 4 ! ! intrq, reset busy !
\ / \-----------------/
+---+ write sector
! 3 ! sequence
\ /
!
+-----------+----------+
! delay 2 bytes of gap !
+----------------------+
! set drq !
+----------------------+
! delay 9 bytes of gap !
+-----------+----------+
!
+----+----+
/ has DR \
! been loaded !
\ (DRQ= 0) /
+----+----+
!yes
+-----------+----------+
! delay 1 byte of gap !--------------+
+-----------+----------+ !
+--+--+
no / is \
+------<-------------! notDDEN !
! \ = 0 ? /
! +--+--+
+-------+-------+ !yes
! turn on wg & ! +--------+--------+
! write 6x 00 ! ! delay 11 bytes !
+-------+-------+ +--------+--------+
! !
+---------+---------+ +-------+-------+
! write data AM !--<----! turn on wg & !
! according to a0 ! ! write 12x 00 !
! bit of write cmd ! +---------------+
+---------+---------+
!
+---------->-----+
! !
! +---------+---------+
! ! DR to DSR,set DRQ !
! +-------------------+
! ! write byte to DSR !
! +---------+---------+
! !
! +---+---+
! / has \ no +---------------+
! ! dr been !--->-! set data lost !
! ! loaded ! ! write 1x 00 !
! \ (drq= 0)/ +-------+-------+
! +---+---+ !
! !yes !
! +--------<----------+
! !
! +----+----+
! no / have all \ yes
+---<-----! bytes been !----->--+
\ assembled / !
+----+----+ +------+------+
! write crc !
+-------------+
! write 1x FF !
+-------------+
! turn off wg !
+------+------+
!
+-+-+
! 5 !
\ /
TYPE 3
!
+---<--------+
! !
+--+--+ !
/is this\ no !
! a write !---->--+
\ track /
+--+--+
!yes
+-----------+-----------+
! set busy, reset drq, !
! lost data (bit 4,5) !
+-----------+-----------+
!
+-+-+
/ is \ no
! h = 1 !------->-----+
\ ? / !
+-+-+ !
!yes !
+--------+--------+ !
! set MO, wait 6 ! !
! index pulses ! !
+--------+--------+ !
! !
+-----<-----------+
!
+-+-+
/ is \ no
! E = 1 !--------->------+
\ ? / !
+-+-+ !
!yes !
+----<-------+ !
! ! !
+---+---+ ! !
/ has \ no ! !
! 30msec !--->--+ !
\ expired / !
+---+---+ !
!yes !
+-------<------------+
! +------->--+----<-------+
+---+---+ ! ! !
/ is \ yes /-------------\ ! +-----+----+ !
! notWPRT !----->--! intrq, reset ! ! / has \ no !
\ = 0 ? / ! busy set wprt ! ! ! index pulse !--->-+
+---+---+ \-------------/ ! \ occurred /
!no ! +----+----+ +---+
+-------+-------+ ! !yes ! A !
! set DRQ ! ! ! \ /
+-------+-------+ ! ! !
! ! !---<--------+
+-------+-------+ ! !
! delay 3 byte ! ! +-----+-----+
! times ! ! ! DR to DSR !
+-------+-------+ ! +-----+-----+
! ! !
+--+--+ /----------------\ ! +-----+-----+
/ has \ no ! intrq, set lost ! ! ! set DRQ !
! DRQ been!--->-! data, reset busy ! ! +-----+-----+
\service/ \----------------/ ! !
+--+--+ ! +-+-+
!yes ! ! B !
+---------------------->---------+ \ /
+---+
! B !
\ /
!
+--+--+
no (FM) / is \ yes (MFM)
+-------<-------------! notDDEN !---------------->--------+
! \ = 0 ? / !
! +--+--+ !
+--+--+ +--+--+
/ is \ yes +-----------+ +---------------+ yes / is \
! DSR=$F7 !--->-! wt 2x CRC !->-+-<-! wt A1 in MFM, !-<---! DSR=$F5 !
\ ? / ! CLK = FF ! ! ! missing CLK, ! \ ? /
+--+--+ +-----------+ ! ! init CRC ! +--+--+
!no ! +---------------+ !no
+--+--+ ! +--+--+
/ is \ yes +-----------+ ! +---------------+ yes / is \
! DSR=$FC !--->-! write FC, !->-+-<-! wt C2 in MFM, !-<---! DSR=$F6 !
\ / ! CLK = F7 ! ! ! with ! \ ? /
+--+--+ +-----------+ ! ! missing CLK ! +--+--+
!no ! +---------------+ !no
+--+--+ +-----------+ ! +--+--+
/is DSR \ yes ! wt FD,FE, ! ! +---------------+ yes / is \
! FD,FE or!--->-! F8-FB,CLK !->-+-<-! generate !-<---! DSR=$F7 !
\ F8-FB / !=C7,initCRC! ! ! 2 bytes CRC ! \ /
+--+--+ +-----------+ ! +---------------+ +--+--+
!no ! !no
+----+----+ ! +----+----+
! wt DSR, !------------->-------+----<--------------------! wt DSR !
! CLK=$FF ! ! ! in MFM !
+---------+ +----<--------------+ +---------+
! !
+---+---+ !
/------------\ yes / phys \ !
! intrq, reset !-<---! index mark! !
! busy flag ! \ ? / !
\------------/ +---+---+ !
! !
+---+---+ !
yes / has DSR \ no +-------+-------+
+---<-------! been !--->-! wt 1x 00 !
! \ loaded ?/ ! set data lost !
+-+-+ +-------+ +---------------+
! A !
\ /